1. Field of the Invention
The present invention relates to a method for forming wells of a semiconductor device, and more particularly to such a method capable of reducing the topology between twin wells of a highly integrated semiconductor device such as CMOS, thereby improving the wiring reliance of the semiconductor device.
2. Description of the Prior Art
In conventional CMOS twin tub structures having twin wells, a p-well region is formed in a self-aligned fashion using an oxide film, grown by an oxidation treatment upon forming an n-well region, as a mask. As result, the substrate has a topology between the p and n wells.
This will be described in detail in conjunction with a conventional method for forming wells of semiconductor devices. FIGS. 1A to 1E illustrate sequential steps of the conventional method for forming wells of a semiconductor device, respectively.
In accordance with this method, a p type silicon substrate 10 is prepared. As shown in FIG. 1A, a thermal oxide film 12 is formed over the p type silicon substrate 10 to a thickness of 100 .ANG.. Over the thermal oxide film 12, Si.sub.3 N.sub.4 is deposited to a thickness of 1,400 .ANG. using a low pressure chemical vapor deposition (LPCVD) process in order to form a silicon nitride film 14.
Thereafter, the silicon nitride film 14 is etched at its portion corresponding to a region where an n well will be formed, using a mask which is constituted by a photoresist film pattern 16 formed on the silicon nitride film 14, thereby forming its pattern defining the n well region, as shown in FIG. 1B. Phosphorus ions are then implanted in the n well region in a density of 1.0.times.10.sup.13 ions/cm.sup.2 using energy of 120 KeV. After the ion implantation, the photoresist film pattern 16 is removed. The resulting structure is then annealed for its drive-in.
As a result, an n well 18 is formed in the silicon substrate, as shown in FIG. 1C. An oxide film 20 having a thickness of 4,500 .ANG. fit is also formed over the n well 18.
Thereafter, the resulting structure is dipped in a hot solution of H.sub.3 PO.sub.4 so as to remove the remaining silicon nitride film 14 disposed at a region where a p well will be formed, as shown in FIG. 1D. Boron ions are then implanted in the p well region in a density of 5.0.times.10.sup.12 ions/cm.sup.2 using energy of 80 KeV. The resulting structure is then annealed at a temperature of 1,150.degree. C. for 4 hours for its drive-in. As a result, a p well 22 is formed in the silicon substrate.
Upon forming the p well 22, the oxide film 20 of 4,500 .ANG. of disposed over the n well 18 is used as an ion implantation mask.
The resulting structure is then dipped in a solution of HF so as to remove the remaining oxide films 12 and 20, as shown in FIG. 1E. Thus, the well formation is completed. The structure is subsequently treated in accordance with the typical process for fabricating CMOS's. Since this subsequent treatment is well known, its description is omitted.
Taking into consideration the fact that the oxide film grown upon forming the n well has a thickness of about 4,000 .ANG., a topology d of about 2,000 .ANG. is formed between the n well 18 and p well 22 even though the substrate is reduced in thickness by about 50% of the thickness of the grown oxide film during the oxidation treatment.
Where a photoresist film is coated over the structure having such topology to form a pattern which will be used for a subsequent processing step, it involves a variation in thickness due to the topology. The variation in thickness ranges up to 10 .mu.m at the boundary between the wells. As a result, the pattern has a dimension varied by 0.1 .mu.m or above after the pattern forming step.
In conventional structures, there is no problem when the variation in dimension is within 10% of the width of the pattern, that is, when the width of the pattern is at least 1.0 .mu.m. Where the variation in dimension depending on the thickness of the photoresist film is more than 0.1 .mu.m as semiconductor devices have a higher integration degree requiring a smaller pattern width of sub-microns less than 1.0 .mu.M, however, there is a disadvantage that a critical circuit having a topology of less than 10 .mu.m at the boundary of wells cannot be designed because the general design tolerance given for the semiconductor devices is more than 10%.
Such a limitation on design serves as a handicap to the fabrication of a circuit for suppressing the latch-up being problematic in highly integrated semiconductor devices. For this reason, it is difficult to obtain highly integrated semiconductor devices.
FIG. 2 illustrates a DRAM device having the above-mentioned CMOS twin well structure. As shown in FIG. 2, the DRAM device typically includes a memory cell 28 formed over the p well 22 and a peripheral drive circuit 30 formed over the n well 18. The memory cell includes an n-MOS transfer transistor 24 and a capacitor 26 in the case of the twin well structure in which the p well is formed in a self-aligned fashion using the oxide film, grown by the oxidation treatment upon forming the n well, as a mask as mentioned above.
In this structure, however, the topology between the memory cell region (including the p-well region 28) and the peripheral circuit region (including the n-well region 30) formed at the step followed by the wiring step is further increased because the capacitor 26 is additionally mounted on the p well 22 disposed at a higher level than the n well 18. Typically, the topology d' between the memory cell region 28 and the peripheral circuit region 30 is at least about 5,000 .ANG. after the semiconductor device is completely fabricated.
Such a severe topology results in a limitation in the depth of focus used in a light exposing device upon carrying out a photolithography process for forming a wiring. As a result, a photoresist film formed for providing a wiring pattern is inaccurately etched upon forming the wiring pattern. That is, the photoresist film is not etched at its portion beyond the limited depth of focus. Due to the unnecessarily remaining portion of the photoresist film, it is difficult to obtain a desired wiring pattern. Where the wiring pattern is varied in width due to the topology, the above-mentioned phenomenon becomes more severe. As a result, the characteristic of the final semiconductor device is degraded.
In order to solve such problems, a more sophisticated method such as a modified illumination method or a multilayered resist (MLR) method has been used which degrades the productivity, thereby making it impossible to achieve the mass production.
Meanwhile, highly integrated semiconductor devices have used a multistacked structure or cylindrical structure in place of the conventional, simple stack capacitor structure in order to obtain a capacitance equal to those of conventional structures while reducing the unit cell area. However, the use of such structures involves the above-mentioned problems because the topology between n- and p-well regions is greatly increased.
For example, in the case of 64-Mega grade DRAM devices having the cylindrical capacitor structure, it is difficult to easily perform the wiring forming step because the topology caused by the capacitor structure is too large, for example, at least 5,000 .ANG.. Due to such a large topology, a variation in dimension occurs at the wiring pattern. This results in a stress concentration at a conduction layer formed on the structure having the large topology and a non-uniformity of the wiring pattern. As a result, there is a degradation in the reliance of the wiring.